FIG. 1 is a conventional CMOS SRAM cell 100. During write 0 access, in which 0 is written into cell 100, bit line BL is driven low, while bit line BLB is driven high. Due to process defects, it may take the node XY a relatively long time to charge to a desired voltage level by charging through a device P1 coupled with a resistor R1 (typically in the range of Mega ohms). If read access is performed soon after the write access, cell 100 may not yet be stabilized and may flip, thus causing the read to fail. This defective condition is referred to as “read disturb,” which may cause yield loss during speed test for packaged devices.
Read disturb failure may not be easily captured at wafer sort, which is a test performed after an integrated circuit is produced but before it is packaged. This is because wafer sort is usually performed at relatively slow speed, which gives the SRAM cell node sufficient time to charge to a desired voltage level. But once the devices are packaged and subjected to speed test (e.g., read operations followed soon after a write operation), read disturb failure may occur, causing yield loss.